1. Field of the Invention
The present invention relates generally to methods and apparatus for detecting light energy using light sensitive devices such as charge-coupled devices (CCDs), and in particular to methods and apparatus for accurately detecting light signals using a charge-coupled device imaging array formed with interline transfer type pixels.
2. State of the Art
Charge-coupled device imaging arrays which use interline transfer pixels are known. These imaging arrays typically integrate (i.e., collect or accumulate) photocharge using photoelements such as polysilicon photogates, photodiodes or pinned photodiodes. A vertical shift register (e.g., charge-coupled device) is typically used to transfer the accumulated photocharge to a read-out device. Charge-coupled device imaging arrays are useful for detection applications such as imaging and laser radar.
FIG. 1 illustrates a typical interline transfer pixel 100 for use in a conventional charge-coupled device. A photocharge accumulation area 102 is illustrated in FIG. 1 as a photogate of length L. Charge accumulated in the photocharge accumulation area is transferred to a vertical shift register 104 which includes polysilicon gates 106. For purposes of illustration, the charge-coupled device vertical shift register 104 is four phase, although any number of such phases can be used.
In a conventional array of interline transfer pixels as shown in FIG. 1, pixels are separated by an exposure control/anti-blooming drain 108 which runs vertically through a column of pixels. An exposure control/anti-blooming structure, such as a polysilicon metal-oxide semiconductor (MOS) gate and a diode can be provided for each interline transfer pixel. In the exemplary FIG. 1 embodiment, a buried drain with self-aligned p-type and n-type implants can be used for exposure control as the anti-blooming drain 108. Thus, the exemplary FIG. 1 embodiment illustrates a lateral anti-blooming structure which includes a buried drain created by self-aligned p-type and n-type implants (i.e., a buried drain), and further including a photogate type photocharge accumulation area.
Metal buses, such as metal bus 110, run throughout a column above the vertical shift register 104. By rendering the metal buses opaque, the vertical shift register can be shielded from light to prevent additional photocharge from being accumulated therein. The metal buses are also used to bring clock signals to the gates of the vertical shift register via contacts 112. Channel stop regions, represented as channel stops 114, can be included to vertically delineate the pixels of the imaging array illustrated in FIG. 1. Thus, the exemplary FIG. 1 embodiment represents the use of an opaque layer of metal to cover the entire circuit with the exception of the light sensitive photocharge accumulation area 102 within each pixel.
FIG. 2 illustrates potentials beneath the FIG. 1 pixel during a charge transfer from the photocharge accumulation area 102 to the vertical shift register 104 via cross-sectional area A-A' in FIG. 1. A gate 116 of the vertical shift register is set to a high voltage bias relative to the voltage bias of the photogate 118 in the photocharge accumulation area 102. Photocharge accumulated in the photogate 118 therefore flows from the photogate into the gate 116 of the vertical shift register as illustrated.
A potential of a buried drain 120 corresponding to the anti-blooming drain 108 of FIG. 1 is set to the same potential as that of a channel under the photogate 118. A barrier 122 in the buried drain 120 prevents charge under the photogate 118 from flowing into the buried drain 120.
Fringe fields in a region under the photogate 118 do not significantly affect photocharge near the center and far edges of the photogate 118. Where charge packets accumulated in the photogate 118 are relatively large, self-repulsion will transfer a significant portion of the photocharge stored therein across the length L to the vertical shift register (i.e., to the gate 116). Thermal diffusion will then transfer any remaining charge in the photogate across the length L of the photogate into the gate 116 of the vertical shift register.
The length L of the photogate 118 in FIG. 2 and the photocharge accumulation area 102 in FIG. 1 (i.e., the distance from a far lateral edge of the photocharge accumulation area 102 adjacent the antiblooming drain 108, to the gate 106 of the vertical shift register 104) is relatively long to provide an adequate pixel pitch for low energy laser pulse detection. However, increased distance of the photocharge accumulation area can significantly affect performance since photocharge accumulated in the photogate 118 is transferred relatively slowly across the distance L into the gate 116, and requires that the charge-coupled device be clocked at a relatively slow rate to provide adequate charge transfer efficiency (CTE). If the pixels of the imaging array are clocked too fast, charge transfer efficiency can be substantially reduced to the point where accurate signal detection is impossible.
Thus, as the lengths of photogates are increased, transfer time can be significantly increased thereby negatively impacting charge transfer efficiency during high speed operation. In pixel arrays operated at high speeds using pixels of relatively large pitch, the photogate length will affect the minimum transfer time and/or affect the charge transfer efficiency. The transfer time can thus become an especially critical factor in high speed exposure control or shuttering. At present, conventional charge-coupled device imaging arrays constructed using interline transfer type pixels as described with respect to FIGS. 1 and 2 are inadequate in addressing the degraded performance which results from high speed operation, and thereby are substantially limited in their ability to provide high speed electronic exposure control or shuttering in applications where accurate signal detection is necessary.